EEG/ERG Signal Generator – Standalone Embedded Hardware Device

Introduction

This project involved designing and implementing a standalone embedded device that generates EEG/ERG signals for laboratory and clinical testing.
The system reads recorded neural signals from an SD card and replays them as precise analog waveforms, enabling reliable test environments for medical and research applications.

Technical Overview

• MCU: Cypress PSoC5 – used for DAC, timers, GPIO, and DMA-based real-time streaming.
• Storage: FAT32-formatted SD card for storing EEG/ERG recording files.
• Signal Generation: Multi-channel DAC output, driven by double buffering and DMA to achieve jitter-free, real-time playback — each channel continuously fed from the recorded EEG file data
• Bootloader: Custom firmware update mechanism triggered by push-button or non-volatile flag, ensuring safe field upgrades.
• Control Logic: State machine managing test sessions, file sequences, repeat counts, and runtime configuration.
• SDK & Automation: Full Python SDK communicating with the device via UART, enabling integration into automated test scripts and lab workflows.
• GUI: Cross-platform Python/PyQt interface that passed formal certification/qualification for regulated lab use.
• Validation Tools: Oscilloscope & logic analyzer used extensively for bring-up, jitter analysis, and signal integrity verification.
• RTOS & Scheduling: Firmware built on FreeRTOS for deterministic task scheduling, separating real-time signal streaming from control and communication tasks.
• Display & User Feedback: Integrated a small LCD to show file playback progress, current session status, and battery level.
• Power & Battery Management: Implemented battery monitoring, charging control, and safe shutdown logic to protect data and hardware.
• CI/CD: Continuous Integration & Deployment pipeline (unit tests + firmware packaging) to ensure reliable updates and reproducible builds.

System Block Diagram

Jitter Verification

• Jitter was measured using a high-resolution oscilloscope and logic analyzer.
• Implemented DMA double buffering and hardware timers, then validated output stability under different SD card loads.
• Stress tested playback with long recordings and fast seek operations to confirm <100 μs max jitter.

Key Features

• Jitter-free real-time playback of EEG/ERG signals using DMA and hardware timers.
• Custom bootloader with safe firmware upgrade logic (trigger via button or NV flag).
• Advanced session control: playlists, loop counts, and dynamic file selection.
• UART-based SDK for PC integration and automation with Python scripts.
• Certified cross-platform GUI for non-technical lab users.
• Low-level hardware bring-up with oscilloscope and logic analyzer to ensure timing accuracy.
• Flexible peripheral integration via GPIO, I²C, SPI, and ADC.

Challenges & Solutions

• Maintaining accurate playback timing: solved by hardware-timed interrupts and DMA double-buffering to avoid CPU-induced jitter.
• Ensuring reliable SD card streaming: implemented large block reads and background buffering to prevent playback gaps.
• Safe firmware updates: developed a dedicated bootloader with a fallback mechanism triggered by user input or non-volatile flags.
• Integrating with lab environments: provided UART-based SDK, GPIO control/status, and Python automation hooks.
• Regulatory compliance: created a GUI that passed formal certification, ensuring usability in controlled lab conditions.

Project Context

Project developed as part of my professional work in the medical device industry (proprietary details omitted).

Outcome

This project evolved from a simple signal replay device into a complete embedded platform: a reliable hardware unit with real-time firmware, safe update mechanism, Python SDK over UART, and a certified GUI. It demonstrates end-to-end embedded development — from low-level drivers and bootloader, through real-time streaming and jitter elimination, to user-friendly integration for lab technicians.